1. Field of the Invention
The present invention relates to a circuit for generating a data row in synchronism with a rate signal having arbitrary time intervals, the circuit being for use in an IC tester etc.
2. Description of the Related Art
FIG. 4 shows an arrangement of a synchronous data row generating circuit of prior art. In FIG. 4, denoted at 10 is a rate generating portion, 20 is a data row generating portion, 20.sub.1 to 20.sub.N are logic circuits, 21.sub.1 to 21.sub.N are D-type flip-flops (referred to as D-type FFs hereinafter), circuits, 22.sub.1 to 22.sub.N are delay elements and 23.sub.1 to 23.sub.N are gates. The logic circuits 20.sub.1 to 20.sub.N, the D-type FFs 21.sub.1 to 21.sub.N, the delay elements 22.sub.1 to 22.sub.N and the gates 23.sub.1 to 23.sub.N constitute the data row generating portion 20.
In FIG. 4, the output of the rate generating portion 10 is connected to the logic circuit 20.sub.1 and delay element 22.sub.1 of the data row generating portion 20. The output of the delay element 22.sub.1 is connected to the gate 23.sub.1. The output of the gate 23.sub.1 is connected to the clock input terminal of the D-type FF 21.sub.1 and the delay element 22.sub.2. Following logic circuits, delay elements, D-type FFs and gates are similarly connected to one another in series.
The timing chart of the synchronous data row generating circuit in FIG. 4 is shown in FIG. 5. FIG. 5 (a) is the waveform diagram of output of the rate generating portion 10, FIG. 5 (b) is that of output of the logic circuit 20.sub.1, FIG. 5 (c) is that of output of the gate 23.sub.1, FIG. 5 (d) is that of output of the D-type FF 21.sub.1 , FIG. 5 (e) is that of output of the gate 23.sub.2, FIG. 5 (f) is that of output of the D-type FF 21.sub.2, FIG. 5 (g) is that of output of a rate signal 12 and FIG. 5 (h) is that of a data row 11 generated by the data row generating portion 20.
In FIG. 5, the rate generating portion 10 generates a desired rate signal having arbitrary time intervals as illustrated in FIG. 5 (a). FIG. 5 (a) exemplifies a case of generating a rate signal having time intervals 40 ns, 50 ns, 60 ns, 40 ns, 50 ns, . . . The output of the rate generating portion 10 is transmitted to the logic circuit 20.sub.1 and the delay element 22.sub.1.
The logic circuit 20.sub.1 generates an arbitrary data row as illustrated in FIG. 5 (b) and supplies the same to the data input terminal of the D-type FF 21.sub.1. The output of the rate generating portion 10 is delayed by the delay element 22.sub.1 to guarantee a setup time and a hold time in the D-type FF 21.sub.1 and is further buffered by the gate 23.sub.1 to be supplied to the clock input terminal of the D-type FF 21.sub.1. The D-type FF 21.sub.1 latches the data row in FIG. 5 (b) in the timing of the delayed rate signal illustrated in FIG. 5 (c) to output a data row illustrated in FIG. 5 (d).
Thereafter the output of the D-type FF 21.sub.1 is processed by the logic circuit 20.sub.2 to be supplied to the data input terminal of the D-type FF 21.sub.2. The D-type FF 21.sub.2 latches the output of the logic circuit 20.sub.2 in the timing of a rate signal which has been delayed by the delay element 22.sub.2 and further buffered by the gate 23.sub.1, as illustrated in FIG. 5 (e) to output a data row as illustrated in FIG. 5 (f).
In a like manner, a data row is generated as illustrated in FIG. 5 (h) in synchronism with a rate signal as illustrated in FIG. 5 (g) while synchronizing the data row with the rate signal by way of the logic circuits, delay elements, gates, and D-type FFs which are connected to one another in series.
In a synchronous data row generating circuit having an arrangement illustrated in FIG. 4, the data row is generated by delaying the rate signal through the delay elements in accordance with the delay time of the logic circuit which generates the data row so as to synchronize the rate signal with the data row having arbitrary time intervals, so that it is necessary to adjust a plurality of delay elements taking into consideration the variation of elements or that of the D-type FFs in setup time or hold time.